Specifications
ispLSI 2064E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
2
4
#
COND.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
DESCRIPTION
1
-200
–
–
200
1
tsu2 + tco1
-135
–
–
135
100
143
5.0
–
0.0
6.0
–
0.0
–
5.0
–
–
–
–
3.5
3.5
7.5
10.0
–
–
–
–
4.0
–
–
4.5
–
10.0
–
12.0
12.0
7.0
7.0
–
–
–
–
-100
10.0
13.0
–
–
–
–
5.0
–
–
6.0
–
13.5
–
15.0
15.0
9.0
9.0
–
–
MIN. MAX. MIN. MAX. MIN. MAX.
4.5
7.0
–
–
–
–
3.0
–
–
3.5
–
6.0
–
8.0
8.0
4.0
4.0
–
–
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
1.
2.
3.
4.
1 Data Prop Delay, 4PT Bypass, ORP Bypass
2 Data Prop Delay
3 Clk Freq with Internal Feedback
3
4 Clk Freq with External Feedback
(
5 Clk Frequency, Max. Toggle
6 GLB Reg Setup Time before Clk, 4 PT Bypass
7 GLB Reg Clk to Output Delay, ORP Bypass
8 GLB Reg Hold Time after Clk, 4 PT Bypass
9 GLB Reg Setup Time before Clk
10 GLB Reg Clk to Output Delay
11 GLB Reg Hold Time after Clk
12 External Reset Pin to Output Delay
13 External Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 External Synch Clk Pulse Duration, High
19 External Synch Clk Pulse Duration, Low
100
77
100
6.5
–
0.0
8.0
–
0.0
–
6.5
–
–
–
–
5.0
5.0
)
133
200
3.5
–
0.0
4.5
–
0.0
–
3.5
–
–
–
–
2.5
2.5
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
Table 2-0030A/2064E
5
LATTICE [ LATTICE SEMICONDUCTOR ]
