Specifications ispGDX160V/VA
ispGDX Development System (Continued)
The ispGDX Design System Compiler
Third-Party Timing Simulation
After the GDF file is created, the compiler checks the The ispGDX Design System will generate simulation
syntax and provides helpful hints and the location of any netlists as specified by a user. The simulation netlist
syntaxerrors. Thecompilerperformsdesignrulechecks, formats available are: EDIF, Verilog (OVI compliant),
such as, clock and enable designations, the use of input/ VHDL (VITAL compliant), Viewlogic, and OrCAD.
output/BIDI usage, and the proper use of attributes. I/O
For In-System Programming, Lattice’s ispGDX devices
may be programmed, alone or in a chain with up to 100
other Lattice ISP devices, using Lattice’s ISP Daisy
ChainDownloadsoftware.ThispowerfulWindows-based
connectivity is also checked to ensure polarity, MUX
selection controls, and connections are properly made.
Compilation is completed automatically and report and
programming files are saved.
tool can be launched from the Tool Bar or by Invoking the
Download option from the drop down menu within the
ispGDX Design System. ISP Daisy Chain Download
Reports Generated
When the ispGDX system compiles a design and gener-
ates the specified netlists, the following output files are
created:
version 7.1 or above supports the ispGDX Family de-
vices.
Report Files:
.log
.rpt
.mfr
.tsu
.tco
.tpt
Compiler History
Compiler Report
Maximum Frequency Timing Report
Set-up and Hold Timing Report
Clock to Out Timing Report
Timing Report
Simulation File:
.sim
Post-Route Simulation With LAC Format
Netlists:
.edo EDIF Output
.vlo
.ifo
Verilog Output
OrCAD Output
.vho VHDL non-VITAL with Maximum Delays Output
.vhn VHDL non-VITAL with Maximum Delays Output
.vto
VHDL VITAL Output
Download:
.jed
JEDEC Device Programming File
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LATTICE [ LATTICE SEMICONDUCTOR ]
