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GAL16VP8B-15LP 参数 Datasheet PDF下载

GAL16VP8B-15LP图片预览
型号: GAL16VP8B-15LP
PDF下载: 下载PDF文件 查看货源
内容描述: 高速E2CMOS PLD通用阵列逻辑 [High-Speed E2CMOS PLD Generic Array Logic]
分类和应用: 可编程逻辑器件光电二极管输入元件时钟
文件页数/大小: 17 页 / 214 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL16VP8  
Complex Mode  
All macrocells have seven product terms per output. One prod-  
uct term is used for programmable output enable control. Pins 1  
and 10 are always available as data inputs into the AND array.  
In the Complex mode, macrocells are configured as output only or  
I/O functions.  
Up to six I/Os are possible in this mode. Dedicated inputs or outputs  
can be implemented as subsets of the I/O function. The two outer  
most macrocells (pins 11 & 19) do not have input capability. De-  
signs requiring eight I/Os can be implemented in the Registered  
mode.  
The JEDEC fuse numbers including the UES fuses and PTD fuses  
are shown on the logic diagram on the following page.  
Combinatorial I/O Configuration for Complex Mode  
- SYN=1.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1 has no effect on this mode.  
- AC2=1 defines totem pole output.  
- AC2=0 defines open-drain output.  
- Pin 12 through Pin 18 are configured to this function.  
XOR  
Combinatorial Output Configuration for Complex Mode  
- SYN=1.  
- AC0=1.  
- XOR=0 defines Active Low Output.  
- XOR=1 defines Active High Output.  
- AC1 has no effect on this mode.  
- AC2=1 defines totem pole output.  
- AC2=0 defines open-drain output.  
- Pin 11 and Pin 19 are configured to this function.  
XOR  
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.  
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