Specifications GAL16VP8
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic each macrocell controls the polarity of the output in any of the three
macrocell. It should be noted that actual implementation is accom- modes, while theAC1 andAC2 bit of each of the macrocells controls
plished by development software/hardware and is completely trans- the input/output and totem-pole/open-drain configuration. These
parent to the user.
two global and 24 individual architecture bits define all possible con-
figurations in a GAL16VP8. The information given on these archi-
There are three global OLMC configuration modes possible: tecture bits is only to give a better understanding of the device.
simple, complex, and registered. Details of each of these modes Compiler software will transparently set these architecture bits from
is illustrated in the following pages. Two global bits, SYN andAC0, the pin definitions, so the user should not need to directly manipulate
control the mode configuration for all macrocells. The XOR bit of these architecture bits.
Compiler Support for OLMC
Software compilers support the three different global OLMC modes In complex mode pin 1 and pin 10 become dedicated inputs and
as different device types. Most compilers also have the ability to use the feedback paths of pin19 and pin 11 respectively. Because
automatically select the device type, generally based on the register of this feedback path usage, pin19 and pin 11 do not have the
usage and output enable (OE) usage. Register usage on the device feedback option in this mode.
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the In simple mode all feedback paths of the output pins are routed
software to choose the complex mode. The software will choose via the adjacent pins. In doing so, the two inner most pins ( pins
the simple mode only when all outputs are dedicated combinatorial 14 and 16) will not have the feedback option as these pins are
without OE control. For further details, refer to the compiler soft- always configured as dedicated combinatorial output.
ware manuals.
In addition to the architecture configurations, the logic compiler
When using compiler software to configure the device, the user software also supports configuration of either totem-pole or open-
must pay special attention to the following restrictions in each mode. drain outputs. The actual architecture bit configuration, again, is
In registered mode pin 1 and pin 10 are permanently configured transparent to the user with the default configuration being the
as clock and output enable, respectively. These pins cannot be con- standard totem-pole output.
figured as dedicated inputs in the registered mode.
3
LATTICE [ LATTICE SEMICONDUCTOR ]
