DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LVDS25E
The top and bottom sides of LatticeECP2/M devices support LVDS outputs via emulated complementary LVCMOS
outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one
possible solution for point-to-point signals.
Figure 3-1. LVDS25E Output Termination Example
VCCIO = 2.5V ( 5%)
RS=158 ohms
( 1%)
8 mA
+
-
RP = 140 ohms
( 1%)
RT = 100 ohms
( 1%)
VCCIO = 2.5V ( 5%)
8 mA
RS=158 ohms
( 1%)
Transmission line, Zo = 100 ohm differential
OFF-chip ON-chip
ON-chip
OFF-chip
Table 3-2. LVDS25E DC Conditions
Parameter
Description
Typical
2.50
20
Units
V
V
Output Driver Supply (+/-5%)
Driver Impedance
CCIO
OUT
Z
Ω
R
R
R
Driver Series Resistor (+/-1%)
Driver Parallel Resistor (+/-1%)
Receiver Termination (+/-1%)
Output High Voltage
158
Ω
S
140
Ω
P
100
Ω
T
V
V
V
V
1.43
1.07
0.35
1.25
100.5
6.03
V
OH
OL
OD
CM
BACK
Output Low Voltage
V
Output Differential Voltage
Output Common Mode Voltage
Back Impedance
V
V
Z
Ω
I
DC Output Current
mA
DC
LVCMOS33D
All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external
resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3V
VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to
4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D.
3-12
LATTICE [ LATTICE SEMICONDUCTOR ]
