DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
sysI/O Single-Ended DC Electrical Characteristics
V
V
IH
IL
Input/Output
Standard
V
V
OH
Min. (V)
OL
Min. (V)
Max. (V)
Min. (V)
Max. (V)
Max. (V)
I
1 (mA)
I
1 (mA)
OH
OL
20, 16,
12, 8, 4
-20, -16,
-12, -8, -4
0.4
V
V
V
V
V
V
V
- 0.4
- 0.2
- 0.4
- 0.2
- 0.4
- 0.2
- 0.4
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
LVCMOS 3.3
LVTTL
-0.3
0.8
2.0
3.6
0.2
0.1
-0.1
20, 16,
12, 8, 4
-20, -16,
-12, -8, -4
0.4
-0.3
-0.3
-0.3
0.8
0.7
2.0
1.7
3.6
3.6
3.6
0.2
0.1
-0.1
20, 16,
12, 8, 4
-20, -16,
-12, -8, -4
0.4
LVCMOS 2.5
LVCMOS 1.8
0.2
0.1
-0.1
16, 12,
8, 4
-16, -12,
-8, -4
0.4
0.35 V
0.35 V
0.65 V
0.65 V
CCIO
CCIO
0.2
0.4
0.2
0.4
0.2
V
V
V
V
V
- 0.2
- 0.4
- 0.2
- 0.4
- 0.2
0.1
8, 4
0.1
6, 2
0.1
1.5
8
-0.1
-8, -4
-0.1
-6, -2
-0.1
-0.5
-8
CCIO
CCIO
CCIO
CCIO
CCIO
LVCMOS 1.5
LVCMOS 1.2
-0.3
-0.3
3.6
3.6
CCIO
CCIO
0.35 V
0.65 V
CC
CC
PCI
-0.3
-0.3
-0.3
0.3 V
0.5 V
3.6
3.6
3.6
0.1 V
0.9 V
CCIO
CCIO
CCIO CCIO
SSTL3 Class I
SSTL3 Class II
V
V
- 0.2
V
+ 0.2
0.7
V
V
- 1.1
- 0.9
REF
REF
REF
REF
CCIO
- 0.2
V
+ 0.2
0.5
16
7.6
12
15.2
20
6.7
8
-16
-7.6
-12
-15.2
-20
-6.7
-8
CCIO
SSTL2 Class I
-0.3
V
V
- 0.18
V
+ 0.18
3.6
0.54
V
- 0.62
REF
REF
CCIO
SSTL2 Class II
SSTL18 Class I
SSTL18 Class II
-0.3
-0.3
-0.3
- 0.18
V
+ 0.18
3.6
3.6
3.6
0.35
0.4
V
V
V
- 0.43
- 0.4
REF
REF
REF
REF
CCIO
CCIO
CCIO
V
- 0.125 V
- 0.125 V
+ 0.125
+ 0.125
REF
REF
V
0.28
- 0.28
11
4
-11
-4
HSTL Class I
-0.3
V
- 0.1
V
+ 0.1
3.6
0.4
V
- 0.4
REF
REF
CCIO
8
-8
8
-8
HSTL18 Class I
HSTL18 Class II
-0.3
-0.3
V
V
- 0.1
- 0.1
V
V
+ 0.1
+ 0.1
3.6
3.6
0.4
0.4
V
V
- 0.4
- 0.4
REF
REF
CCIO
12
16
-12
-16
REF
REF
CCIO
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA, where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
3-10
LATTICE [ LATTICE SEMICONDUCTOR ]
