Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level)
Flexible sysIO Buffers:
LVCMOS, HSTL, SSTL,
LVDS, and other standards
Programmable
Function Units
(PFUs)
Pre-engineered source
synchronous support
• DDR1/2
• SPI4.2
• ADC/DAC devices
sysDSP Blocks
Multiply and
Accumulate Support
Flexible routing optimized
for speed, cost and routability
sysMEM Block RAM
18kbit Dual Port
Configuration logic, including
dual boot and encryption.
On-chip oscillator and
soft-error detection.
sysCLOCK PLLs and DLLs
Frequency Synthesis and
Clock Alignment
Configuration port
Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level)
SERDES
Flexible sysIO
Buffers:
LVCMOS, HSTL
Channel Channel
Channel Channel
1
0
3
2
SSTL, LVDS
Programmable
Function Units
(PFUs)
Pre-Engineered
Source Synchronous
Support
• DDR1/2
• SPI4.2
DSP Blocks
• ADC/DAC devices
Multiply & Accumulate
Support
sysCLOCK SPLLs
Configuration
Logic, Including
dual boot and encryption,
and soft-error detection
Flexible Routing
optimized for speed,
cost & routability
sysCLOCK GPLLs
& GDLLs
sysMEM Block
RAM 18kbit Dual Port
Frequency Synthesis
& Clock Alignment
Configuration Port
On-Chip
Oscillator
2-2
LATTICE [ LATTICE SEMICONDUCTOR ]
