LatticeECP2/M Family Data Sheet
Introduction
June 2008
Data Sheet DS1006
■ Pre-Engineered Source Synchronous I/O
Features
• DDR registers in I/O cells
■ High Logic Density for System Integration
• Dedicated gearing logic
• 6K to 95K LUTs
• 90 to 583 I/Os
• Source synchronous standards support
– SPI4.2, SFI4 (DDR Mode), XGMII
– High Speed ADC/DAC devices
• Dedicated DDR and DDR2 memory support
– DDR1: 400 (200MHz) / DDR2: 533 (266MHz)
• Dedicated DQS support
■ Embedded SERDES (LatticeECP2M Only)
• Data Rates 250 Mbps to 3.125 Gbps
• Up to 16 channels per device
PCI Express, Ethernet (1GbE, SGMII), OBSAI,
CPRI and Serial RapidIO.
■ Programmable sysI/O™ Buffer Supports
Wide Range Of Interfaces
■ sysDSP™ Block
• 3 to 42 blocks for high performance multiply and
accumulate
• LVTTL and LVCMOS 33/25/18/15/12
• SSTL 3/2/18 I, II
• Each block supports
• HSTL15 I and HSTL18 I, II
• PCI and Differential HSTL, SSTL
• LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL
– One 36x36, four 18X18 or eight 9X9 multipliers
■ Flexible Memory Resources
• 55Kbits to 5308Kbits sysMEM™ Embedded
Block RAM (EBR)
■ Flexible Device Configuration
• 1149.1 Boundary Scan compliant
• Dedicated bank for configuration I/Os
• SPI boot flash interface
– 18Kbit block
– Single, pseudo dual and true dual port
– Byte Enable Mode support
• Dual boot images supported
• 12K to 202Kbits distributed RAM
– Single port and pseudo dual port
■ sysCLOCK Analog PLLs and DLLs
• Two GPLLs and up to six SPLLs per device
– Clock multiply, divide, phase & delay adjust
– Dynamic PLL adjustment
• TransFR™ I/O for simple field updates
• Soft Error Detect macro embedded
■ Optional Bitstream Encryption
(LatticeECP2/M “S”Versions Only)
■ System Level Support
• ispTRACY™ internal logic analyzer capability
• On-chip oscillator for initialization & general use
• 1.2V power supply
• Two general purpose DLLs per device
Table 1-1. LatticeECP2 (Including “S-Series”) Family Selection Guide
Device
ECP2-6
ECP2-12
12
ECP2-20
21
ECP2-35
32
ECP2-50
48
ECP2-70
68
LUTs (K)
6
12
Distributed RAM (Kbits)
EBR SRAM (Kbits)
24
42
64
96
136
55
221
12
276
15
332
18
387
21
1032
60
EBR SRAM Blocks
3
sysDSP Blocks
3
6
7
8
18
22
18x18 Multipliers
12
24
28
32
72
88
GPLL + SPLL + DLL
2+0+2
190
2+0+2
297
2+0+2
402
2+0+2
450
2+2+2
500
2+4+2
583
Maximum Available I/O
Packages and I/O Combinations
144-pin TQFP (20 x 20 mm)
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
90
93
131
193
297
131
193
331
402
190
331
450
339
500
500
583
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DS1006 Introduction_01.7
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