Introduction
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Table 1-2. LatticeECP2M (Including “S-Series”) Family Selection Guide
Device
ECP2M20
19
ECP2M35
34
ECP2M50
48
ECP2M70
67
ECP2M100
95
LUTs (K)
sysMEM Blocks (18kb)
Embedded Memory (Kbits)
Distributed Memory (Kbits)
sysDSP Blocks
66
114
225
246
288
1217
41
2101
71
4147
101
4534
145
5308
202
6
8
22
24
42
18x18 Multipliers
24
32
88
96
168
GPLL+SPLL+DLL
2+6+2
304
2+6+2
410
2+6+2
410
2+6+2
436
2+6+2
520
Maximum Available I/O
Packages and SERDES / I/O Combinations
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
1152-ball fpBGA (35 x 35 mm)
4 / 140
4 / 304
4 / 140
4 / 303
4 / 410
4 / 270
8 / 372
8 / 410
16 / 416
16 / 436
16 / 416
16 / 520
Introduction
The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced
DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an
economical FPGA fabric. This combination was achieved through advances in device architecture and the use of
90nm technology.
The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M
devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked
Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced configu-
ration support, including encryption (“S” versions only) and dual boot capabilities.
The LatticeECP2M device family features high speed SERDES with PCS.These high jitter tolerance and low trans-
mission jitter SERDES with PCS blocks can be configured to support an array of popular data protocols including
PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization
settings make SERDES suitable for chip to chip and small form factor backplane applications.
The ispLEVER® design tool suite from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for popular logic synthesis
tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to
place and route the design in the LatticeECP2/M device. The ispLEVER tool extracts the timing from the routing
and back-annotates it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP2/M
family. By using these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of
their design, increasing their productivity.
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