Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Figure 2-4. Slice Diagram
FCO To Different Slice/PFU
SLICE
OFX1
FXB
FXA
F1
A1
B1
C1
D1
CO
F/SUM
D
Q1
LUT4 &
CARRY*
FF*
To
CI
Routing
M1
M0
LUT5
From
Routing
Mux
OFX0
A0
CO
B0
C0
D0
F0
LUT4 &
CARRY*
F/SUM
Q0
D
FF*
CI
CE
CLK
LSR
* Not in Slice 3
FCI From Different Slice/PFU
For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data
WAD [A:D] is a 4bit address from slice 1 LUT input
Table 2-2. Slice Signal Descriptions
Function
Input
Type
Signal Names
Description
Data signal
A0, B0, C0, D0 Inputs to LUT4
A1, B1, C1, D1 Inputs to LUT4
Input
Data signal
Input
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
Inter-PFU signal
Inter-slice signal
Inter-slice signal
Data signals
Data signals
Data signals
Data signals
Inter-PFU signal
M0
M1
Multipurpose Input
Multipurpose Input
Clock Enable
Input
Input
CE
Input
LSR
CLK
FC
Local Set/Reset
Input
System Clock
Fast Carry-in1
Input
Input
FXA
FXB
F0, F1
Q0, Q1
OFX0
OFX1
FCO
Intermediate signal to generate LUT6 and LUT7
Intermediate signal to generate LUT6 and LUT7
LUT4 output register bypass signals
Input
Output
Output
Output
Output
Output
Register outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
Slice 2 of each PFU is the fast carry chain output1
1. See Figure 2-4 for connection details.
2. Requires two PFUs.
2-4
LATTICE [ LATTICE SEMICONDUCTOR ]
