Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Figure 2-16. Secondary Clock Selection
Secondary Clock Feedlines: 8 PIOs + 16 Routing
24:1
24:1
24:1
24:1
24:1
24:1
24:1
24:1
SC0
SC1
SC2
SC3
SC4
SC5
SC6
SC7
4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region
Clock/Control
4 High Fan-out Data Signals (SC4 to SC7) per Region
High Fan-out Data
Slice Clock Selection
Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals can be used
as a clock input to the slices via routing. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-17. Slice0 through Slice2 Clock Selection
Primary Clock
8
Secondary Clock
Clock to Slice
4
12
1
25:1
Routing
Vcc
2-17
LATTICE [ LATTICE SEMICONDUCTOR ]
