Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Secondary Clock/Control Sources
LatticeECP2/M devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the
rest from routing. Figure 2-11 shows the secondary clock sources.
Figure 2-11. Secondary Clock Sources
Clock
Clock
Input
Input
From
From
From
From
Routing Routing
Routing Routing
From Routing
From Routing
From Routing
From Routing
Clock Input
Clock Input
Secondary Clock Sources
Clock Input
Clock Input
From Routing
From Routing
From Routing
From Routing
From
From
From
From
Routing Routing
Routing Routing
Clock
Clock
Input
Input
2-13
LATTICE [ LATTICE SEMICONDUCTOR ]
