Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs/DLLs and clock dividers as shown in Figure 2-12.
Figure 2-12. Edge Clock Sources
Clock Input
Clock Input
From
From
Routing
Routing
Sources for top
edge clocks
From Routing
From Routing
Clock
Input
Clock
Input
Clock
Input
Clock
Input
From Routing
Eight Edge Clocks (ECLK)
Two Clocks per Edge
From Routing
DLLDELA
DLLDELA
DLL
Input
DLL
Input
DLL
DLL
PLL
Input
PLL
Input
GPLL
GPLL
Sources for right edge clocks
Sources for left edge clocks
Sources for
bottom edge
clocks
From
Routing
From
Routing
Clock Input
Clock Input
2-14
LATTICE [ LATTICE SEMICONDUCTOR ]
