Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Figure 2-18. Slice0 through Slice2 Control Selection
Secondary Clock
3
Slice Control
Routing
16:1
12
Vcc
1
Edge Clock Routing
LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the
implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ-
ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the
CLKO signal (generated from the DLLDELA block) is routed to all the edge clock muxes on the left and right sides
of the device. Figure 2-19 shows the selection muxes for these clocks.
Figure 2-19. Edge Clock Mux Connections
Top and Bottom
Clock Input Pad
Routing
Edge Clocks
ECLK1/ ECLK2
(Both Mux)
Input Pad
GPLL Input Pad
Left and Right
Edge Clocks
ECLK1
DLL Output CLKOP
GPLL Output CLKOP
Routing
CLKO
Input Pad
GPLL Input Pad
Left and Right
Edge Clocks
ECLK2
DLL Output CLKOS
GPLL Output CLKOS
Routing
CLKO
2-18
LATTICE [ LATTICE SEMICONDUCTOR ]
