Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Table 2-5. DLL Signals
Signal
I/O
I
Description
CLKI
Clock input from external pin or routing
CLKFB
I
DLL feed input from DLL output, clock net, routing or external pin
Active low synchronous reset
RSTN
I
ALUHOLD
UDDCNTL
DCNTL[8:0]
CLKOP
I
Active high freezes the ALU
I
Synchronous enable signal (hold high for two cycles) from routing
Encoded digital control signals for PIC INDEL and slave delay calibration
The primary clock output
O
O
O
O
CLKOS
The secondary clock output with fine phase shift and/or division by 2 or by 4
Active high phase lock indicator
LOCK
DLLDELA Delay Block
Closely associated with each DLL is a DLLDELA block.This is a delay block consisting of a delay line with taps and
a selection scheme that selects one of the taps. The DCNTL[8:0] bus controls the delay of the CLKO signal. Typi-
cally this is the delay setting that the DLL uses to achieve phase alignment.This results in the delay providing a cal-
ibrated 90° phase shift that is useful in centering a clock in the middle of a data cycle for source synchronous data.
The CLKO signal feeds the edge clock network. Figure 2-7 shows the connections between the DLL block and the
DLLDELA delay block. For more information, please see the list of additional technical documentation at the end of
this data sheet.
Figure 2-7. DLLDELA Delay Block
PLL_PIO
CLKOP
Routing
Routing
CLKI
*
*
DLL_PIO
CLKOS
LOCK
DLL Block
CLKFB_CK
CLKOP
CLKFB
CLKI
GDLLFB_PIO
ECLK1
DCNTL[8:0]
CLKO
DLLDELA Delay Block
*
* Software selectable
PLL/DLL Cascading
LatticeECP2/M devices have been designed to allow certain combinations of PLL (GPLL and SPLL) and DLL cas-
cading. The allowable combinations are:
• PLL to PLL supported
• PLL to DLL supported
2-9
LATTICE [ LATTICE SEMICONDUCTOR ]
