Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.)
LFE2-12E/SE
LFE2-20E/SE
Pin
Number
Pin/Pad
Function
Dual
Function
Pin/Pad
Function
Dual
Function
Bank
Differential
Bank
Differential
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GND
PT28A
PT26B
PT26A
VCC
-
GND
PT37A
PT36B
PT36A
VCC
-
0
0
0
-
PCLKT0_0
T
C
T
0
0
0
-
PCLKT0_0
T
C
T
PT20B
VCCAUX
PT20A
GND
0
-
C
T
PT30B
VCCAUX
PT30A
GND
0
-
C
T
0
-
0
-
PT18B
PT18A
VCCIO0
PT16B
PT16A
VCC
0
0
0
0
0
-
C
T
PT26B
PT26A
VCCIO0
PT20B
PT20A
VCC
0
0
0
0
0
-
C
T
C
T
C
T
PT12B
PT12A
GND
0
0
-
C
T
PT12B
PT12A
GND
0
0
-
C
T
PT8B
0
0
0
0
0
0
0
C
T
C
T
PT8B
0
0
0
0
0
0
0
C
T
C
T
PT8A
PT8A
PT6B
PT6B
PT6A
PT6A
VCCIO0
PT2B
VCCIO0
PT2B
VREF2_0
VREF1_0
C
T
VREF2_0
VREF1_0
C
T
PT2A
PT2A
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
4-30
LATTICE [ LATTICE SEMICONDUCTOR ]
