Specifications ispLSI 8600V
1
External Switching Characteristics
Over Recommended Operating Conditions
-125
-90
-60
PARA- TEST
METER COND.
2
#
DESCRIPTION
UNITS
4
MIN. MAX. MIN. MAX. MIN. MAX.
A
Prop Delay, BFM Input to Same BFM Output, 4 PT Bypass
Prop Delay, Global Input to Global Output
—
—
8.5
13.5
—
—
—
10.0
16.0
—
—
—
15.0
24.0
—
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
pd2
max
suq
hq
1
A
—
—
—
A
2
3
Clk Frequency, Local Feedback, Same GLB 3
I/O Cell Reg, Data Setup Time, Quadrant I/O Clock
I/O Cell Reg, Data Hold Time, Quadrant I/O Clock
I/O Cell Reg, Quadrant Clock to Output Delay
I/O Cell Reg, Data Setup Time, Global Clock
I/O Cell Reg, Data Hold Time, Global Clock
I/O Cell Reg, Global Clock to Output Delay
125.0
5.0
0.0
—
90.0
8.0
0.0
—
60.0
12.0
0.0
—
—
—
4
—
4.0
—
—
—
5
6.0
—
9.0
—
coq
sug
hg
6
—
—
A
3.5
0.0
—
6.0
0.0
—
9.0
0.0
—
7
—
—
—
8
6.0
—
7.5
—
11.0
—
cog
su1
h1
9
—
—
A
GLB Reg Setup, BFM Input to Same BFM GLB, 4 PT Bypass 4.5
7.0
0.0
—
10.0
0.0
—
10
11
12
13
14
15
16
17
18
19
20
21
22
GLB Reg Hold Time, BFM Input to Same BFM GLB
GLB Reg, Global Clock to Same BFM Output Delay
I/O Cell Reg, CLKEN Setup Time, Quadrant I/O Clock
I/O Cell Reg, CLKEN Hold Time, Quadrant I/O Clock
GLB Reg, CLKEN Setup Time, Global Clock
GLB Reg, CLKEN Hold Time, Global Clock
Global Output Enable/Disable Delay
0.0
—
—
—
—
8.0
—
10.0
—
15.0
—
co1
suceq
hceq
suceg
hceg
goe
rglb
rio
—
—
—
—
B/C
—
—
—
—
—
5.5
0.0
3.5
0.0
—
6.5
0.0
4.5
0.0
—
9.5
0.0
6.5
0.0
—
—
—
—
—
—
—
—
—
—
7.0
14.0
8.5
—
10.0
15.0
10.0
—
15.0
22.0
15.0
—
Global Reset/Preset Time, GLB Reg
—
—
—
Global Reset/Preset Time, I/O Cell Reg
—
—
—
Global Reset/Preset Pulse Duration
5.0
4.0
4.0
6.5
6.0
6.0
9.5
9.0
9.0
rw
Global or Quadrant Clock Pulse, High Duration
Global or Quadrant Clock Pulse, Low Duration
—
—
—
wh
—
—
—
wl
Table 2-0030/8600V
1. Unless noted otherwise, all parameters use PTSA and CLK0.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 20-bit counter with local feedback.
4. Refer to Switching Test Conditions section.
14
LATTICE [ LATTICE SEMICONDUCTOR ]
