Specifications ispLSI 8600V
Internal Timing Parameters
Over Recommended Operating Conditions
-125
-90
-60
PARA-
METER
2
#
DESCRIPTION
MIN
MAX
MIN
MAX
MIN
MAX UNITS
BFM / Global Routing Pool Delay
tbfmi
tgrpi
tgrpiz
tbfmm
tgrpm
61 BFM Routing Delay, Signal from I/O Cell
0.4
–
1.0
1.6
4.1
0.6
2.0
3.0
2.5
1.3
1.5
2.3
0.8
1.6
0.6
–
1.3
1.9
4.9
0.7
3.0
4.3
3.3
1.5
1.7
2.6
0.8
1.7
0.8
–
1.9
2.8
7.3
1.1
4.5
6.5
4.9
2.3
2.6
4.0
1.2
2.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
62 GRP Delay, Signal from I/O Cell
63 Internal Tristate Bus Enable/Disable, I/O Cell Buffer
64 BFM Routing Delay, Signal from Macrocell
65 GRP Delay, Signal from Macrocell
–
–
–
–
–
–
–
–
–
tgrpmz 66 Internal Tristate Bus Enable/Disable, Macrocell Buffer
–
–
–
tbfmg
tgrpb
tbcom
tbreg
tgcom
tgreg
67 BFM Routing Delay, Signal from GRP
68 GRP Delay, Signal from BFM Routing
69 BFM Routing to I/O Cell, Combinatorial Path
70 BFM Routing to I/O Cell, Registered Path
71 GRP to I/O Cell, Combinatorial Path
72 GRP to I/O Cell, Registered Path
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I/O Control Bus Delay
tpiock
73 Product Term as I/O Cell Register Clock
–
–
–
–
–
4.1
4.6
5.6
4.3
3.3
–
–
–
–
–
4.7
5.3
6.5
5.0
3.8
–
–
–
–
–
7.2
8.1
9.9
7.6
5.8
ns
ns
ns
ns
ns
tpiocken 74 Product Term as I/O Cell Register Clock Enable
tpoe
tpiorst
tpioz
75 Product Term as Output Buffer Enable/Disable
76 Product Term as I/O Cell Register Reset or Set Delay
77 Internal Tristate Bus Control Signal for I/O Cell Buffer
Global Control Delay
tgck
78 Global Macrocell Register Clk
3.9
6.4
3.4
6.5
1.9
–
4.1
6.4
3.9
6.5
1.9
5.6
8.5
7.6
5.4
4.3
7.5
4.0
7.5
2.0
–
4.9
7.5
4.4
7.5
2.9
8.3
10.1
7.8
6.4
6.6
11.4
6.1
11.4
3.1
–
7.5
11.4
6.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tgcken 79 Global Macrocell Register Clk Enable
tgiock
tgiocken 81 Global I/O Register Clk Enable
tqck
tgoe
ttoe
tgmrst
tgiorst
80 Global I/O Register Clk
11.4
4.5
82 Quadrant I/O Register Clk
83 Global Output Enable
12.4
15.2
11.8
9.6
84 Test Output Enable
–
–
–
85 Global GLB Register Reset
86 Global I/O Cell Register Reset
–
–
–
–
–
–
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
16
LATTICE [ LATTICE SEMICONDUCTOR ]
