Specifications ispLSI 5256VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-125
-100
-70
2
PARAM
#
DESCRIPTION
MIN MAX MIN MAX MIN MAX UNIT
GRP
tgrpi
57
58
GRP Delay from I/O Pad
GRP Delay from Macrocell
–
–
1.5
1.0
–
–
2
–
–
3
ns
ns
tgrpm
1.2
1.2
Global Control Delays
tgclk01
tgclk23
tgclken0
tgclken1
tgrst
59
60
61
62
63
64
65
Global Clock 0 or 1 Delay
Global Clock 2 or 3 Delay
Global CLKEN 0 Delay
Global CLKEN 1 Delay
Global Set/Reset Delay
Global OE Delay
–
–
–
–
–
–
–
1.2
2.2
1.7
2.7
12.2
4.7
4.7
–
–
–
–
–
–
–
1.7
2.7
2.4
3.4
15.8
6.3
6.2
–
–
–
–
–
–
–
2.4
4.4
3.4
5.4
23.4
9.4
9.4
ns
ns
ns
ns
ns
ns
ns
tgoe
ttoe
Test OE Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Timing Rev. 4.0
ispLSI 5256VA Timing Model
Output
Buffer
Input
Buffer
GRP
GLB/Macrocell
I/O
Pad
I/O
Pad
Buffer Delays
Slew
t
t
t
#20
#56
#28
#27
grpm
slsd
slfd
t
t
t
#22
#23
#24
t
odcom
odreg
odz
idcom
t
#37
ftog
t
#55 grpi
#25
#26
t
t
t
PTSA
Register
slf
sls
idreg
#21
OUTPUT
INPUT
t
t
t
t
t
t
#40
#44
#42
#41
#45
#43
5ptcom
ptsacom
5ptxcom
5ptxreg
ptsareg
5ptreg
t
t
t
#29
#30
#32
mbp
mlat
msu
AND Array
#38
t
t
#33
mh
#31
#35
#34
mco
t
andhs
t
t
mhce
msuce
t
andlp
Dedicated
Input Buffers
t
#36
mrst
#39
PT Controls
t
t
t
t
t
t
t
#57
#58
#59
#60
#61
#62
#63
t
gclk0
#49
sck
t
#46 pck
gclk123
gclken0
Input
Pad
t
#50 ptsacken
tpcken
tscken
gclken1
grst
#47
#48
goe
toe
t
#51
srst
t
#52 prst
t
t
#53
#54
poe
gpoe
15
LATTICE [ LATTICE SEMICONDUCTOR ]
