Specifications ispLSI 5256VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-125
-100
-70
2
PARAM
#
DESCRIPTION
MIN MAX MIN MAX MIN MAX UNIT
I/O Buffer
tidcom
tidreg
todcom
todreg
todz
22
23
24
25
26
27
28
29
30
Input Pad and Buffer, Combinatorial Input
Input Pad and Buffer, Registered Input
Output Pad and Buffer, Combinatorial Output
Output Pad and Buffer, Registered Output
Output Buffer Enable/Disable
–
–
–
–
–
–
–
–
–
0.7
4.7
1.3
1.8
1.3
0
–
–
–
–
–
–
–
–
–
0.9
6.6
1.7
2.8
1.7
0
–
–
–
–
–
–
–
–
–
1.4
9.7
2.6
4.6
2.6
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tslf
Slew Rate Adder, Fast Slew
tsls
Slew Rate Adder, Slow Slew
7.5
0.5
8
10
15
1
tslfd
Programmable Delay Adder, Fast Slew
Programmable Delay Adder, Slow Slew
0.7
10.7
tslsd
16
GLB/Macrocell Delay Register
tmbp
31
32
33
34
35
36
37
38
39
Macrocell Register/Latch Bypass
–
–
0
1
1
–
–
–
–
1
1
–
–
0
1.4
1
–
–
0
2
1
–
–
–
–
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
tmlat
Macrocell Latch Delay
tmco
Macrocell Register/Latch Clock to Output
Macrocell Register/Latch Setup Time
Macrocell Register/Latch Hold Time
Macrocell Register/Latch CLKEN Setup Time
Macrocell Register/Latch CLKEN Hold Time
Macrocell Register/Latch Set/Reset Time
Toggle Flip-Flop Feedback
–
–
–
tmsu
1
1.1
3.9
1.4
1.4
–
–
1.7
5.3
2
tmh
2.5
1
–
tmsuce
tmhce
tmrst
–
1
–
2
–
1.4
1.3
–
tftog
–
–
–
AND Array
tandhs
tandlp
PTSA
40
41
AND Array, High Speed Mode
AND Array, Low Power Mode
–
–
3
5
–
–
4
–
–
6
ns
ns
6.6
10
t5ptcom
t5ptreg
t5ptxcom
t5pxtreg
tptsacom
tptsareg
42
43
44
45
46
47
5 Product Term Bypass, Combinatorial
5 Product Term Bypass, Registered
5 Product Term XOR, Combinatorial
5 Product Term XOR, Registered
–
–
–
–
–
–
1
1
–
–
–
–
–
–
1.4
1.7
3.6
2.2
4.1
2.7
–
–
–
–
–
–
2
2.3
5
ns
ns
ns
ns
ns
ns
2.5
1.5
3
3.3
6
Product Term Sharing Array, Combinatorial
Product Term Sharing Array, Registered
2.0
4.3
PTSA Controls
tpck
48
49
50
51
Product Term Clock Delay
–
–
–
–
–
–
–
–
–
0.5
1
–
–
–
–
–
–
–
–
–
0.7
1.4
1.4
0.7
2.4
3.4
2
–
–
–
–
–
–
–
–
–
1
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
tpcken
tscken
tsck
Product Term CLKEN Delay
Shared Product Term CLKEN Delay
Shared Product Term Clock Delay
Product Term Sharing Array CLKEN Delay
Shared Product Term Set/Reset Delay
Product Term Set/Reset Delay
1
2
0.5
2.0
2.5
1.5
2.5
11.5
1
tptsacken 52
4
tsrst
tprst
tpoe
tgpoe
53
54
55
56
5
3
Product Term Output Enable/Disable
Global PT Output Enable/Disable
3.4
15.4
5
17
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Timing Rev. 4.0
14
LATTICE [ LATTICE SEMICONDUCTOR ]
