Specifications
ispLSI 3256E
ispLSI 3256E Timing Model
I/O Cell
GRP
Feedback
#31
GLB
ORP
I/O Cell
I/O Pin
(Input)
I/O Reg Bypass
#24
Input
D Register Q
RST
#25 - 29
GRP
#30
4 PT Bypass
#32
20 PT
XOR Delays
#33 - 35
#52
GLB Reg Bypass
#36
GLB Reg
Delay
D
RST
Q
#37 - 40
ORP Bypass
#45
ORP
Delay
#44
#46, 47
I/O Pin
(Output)
#52
Reset
Y3,4
#48, 49
#51
Control RE
PTs
OE
#41 - 43 CK
Y0,1,2
#50
GOE0,1
TOE
#53
#54
0902/3256E
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
t
su
=
=
=
1.4 ns =
=
=
=
4.5 ns =
=
=
=
13.7 ns =
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
iobp +
t
grp +
t
ptck(min))
(#24+ #30+ #34) + (#37) - (#24+ #30+ #43)
(2.4 + 2.3 + 4.1) + (0.3) - (2.4 + 2.3 + 3.0)
Clock (max) + Reg h - Logic
(
t
iobp +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
iobp +
t
grp +
t
20ptxor)
(#24+ #30+ #43) + (#38) - (#24+ #30+ #34)
(2.4 + 2.3 + 3.6) + (5.0) - (2.4 + 2.3 + 4.1)
Clock (max) + Reg co + Output
(
t
iobp +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#24 + #30 + #43) + (#39) + (#44 + #46)
(2.4 + 2.3 + 3.6) + (1.6) + (1.2 + 2.6)
Table 2- 0042-3256E
t
h
t
co
Note: Calculations are based upon timing specifications for the ispLSI 3256E-100L.
9
LATTICE [ LATTICE SEMICONDUCTOR ]
