Specifications
ispLSI 3256E
External Switching Characteristics
1, 2, 3
Over Recommended Operating Conditions
PARAMETER
TEST
5
COND.
#
2
DESCRIPTION
1
-100
—
—
100
77.0
100
5.5
—
0.0
6.5
—
0.0
—
6.5
—
—
—
—
—
—
5.0
5.0
4.5
0.0
10.0
13.0
—
—
—
—
6.5
—
—
7.0
—
13.5
—
16.0
16.0
9.0
9.0
12.0
12.0
—
—
—
—
—
—
-70
15.0
18.0
—
—
—
—
9.0
—
—
10.0
—
15.0
—
19.0
19.0
12.0
12.0
15.0
15.0
—
—
—
—
MIN. MAX. MIN. MAX.
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
toeen
t
toedis
t
wh
t
wl
t
su3
t
h3
1.
2.
3.
4.
5.
A
A
A
—
—
—
A
—
—
—
—
A
—
B
C
B
C
—
—
—
—
—
—
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
2 Data Propagation Delay
3 Clock Frequency with Internal Feedback
3
4 Clock Freq. with Ext. Feedback,1/(tsu2 + tco1)
5 Clock Frequency, Max Toggle
4
6 GLB Reg. Setup Time before Clock, 4PT bypass
7 GLB Reg. Clock to Output Delay, ORP bypass
8 GLB Reg. Hold Time after Clock, 4PT bypass
9 GLB Reg. Setup Time before Clock
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 Test OE Output Enable
19 Test OE Output Disable
20 Ext. Sync. Clock Pulse Duration, High
21 Ext. Sync. Clock Pulse Duration, Low
22 I/O Reg. Setup Time before Ext. Sync. Clock (Y3, Y4)
23 I/O Reg. Hold Time after Ext. Sync. Clock (Y3, Y4)
70.0
50.0
83.0
9.0
—
0.0
11.0
—
0.0
—
12.0
—
—
—
—
—
—
6.0
6.0
5.0
0.0
Unless noted otherwise, all parameters use 20 PTXOR path and ORP.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions section.
Timing Ext.3256E.eps
6
LATTICE [ LATTICE SEMICONDUCTOR ]
