Specifications
ispLSI 3256E
Internal Timing Parameters
1
Over Recommended Operating Conditions
PARAMETER
#
2
DESCRIPTION
-100
MIN.
—
—
—
—
1.6
0.3
—
—
—
MAX.
2.6
17.6
5.5
5.5
1.6
1.6
4.5
5.9
6.1
-70
MIN.
—
—
—
—
1.8
0.8
—
—
—
MAX.
3.3
18.3
5.7
5.7
1.8
2.5
4.6
7.5
8.9
UNITS
Outputs
t
ob
t
obs
t
oen
t
odis
Clocks
46 Output Buffer Delay
47 Output Buffer Delay, Slew Limited Adder
48 I/O Cell OE to Output Enabled
49 I/O Cell OE to Output Disabled
50 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clk Line
51 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line
52 Global Reset to GLB and I/O Registers
53 Global OE Pad Buffer
54 Test OE Pad Buffer
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
gy0/1/2
t
ioy3/4
Global Reset
t
gr
t
goe
t
toe
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Timing Int.2.3256E.eps
8
LATTICE [ LATTICE SEMICONDUCTOR ]
