Specifications
ispLSI 1048EA
ispLSI 1048EA Timing Model
I/O Cell
GRP
#47
Ded. In
GLB
Feedback
#34
GRP4
#30
GRP Loading
Delay
#29, 31 - 33
Comb 4 PT Bypass
GLB Reg Bypass
#39
GLB Reg
Delay
D
RST
Reset
#60
#40 - 43
Q
ORP Bypass
#49
ORP
Delay
#48
#50, 51
I/O Pin
(Output)
ORP
I/O Cell
#28
I/O Reg Bypass
#22
Input
D Register Q
RST
#23 - 27
I/O Pin
(Input)
Reg 4 PT Bypass
#35
20 PT
XOR Delays
#36 - 38
#52, 53
#60
Clock
Distribution
Y1,2,3
#56 - 59
Control RE
PTs
OE
#44 - 46 CK
0491/1048EA
Y0
GOE 0,1
#55
#54
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
t
su
=
=
=
0.8 =
=
=
=
2.5 =
=
=
=
7.9 =
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) - (
t
iobp +
t
grp4 +
t
ptck(min))
(#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
(0.3 + 1.6 + 2.2) + (0.3) - (0.3 + 1.6 + 1.7)
Clock (max) + Reg h - Logic
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gh) - (
t
iobp +
t
grp4 +
t
20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 1.6 + 2.7) + (2.0) - (0.3 + 1.6 + 2.2)
Clock (max) + Reg co + Output
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#22 + #30 + #46) + (#42) + (#48 + #50)
(0.3 + 1.6 + 2.7) + (1.4) + (1.0 + 0.9)
t
h
t
co
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
t
su
=
=
=
1.3 =
=
=
=
2.0 =
=
=
=
7.4 =
Logic + Reg (setup) - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) - (
t
gy0(min) +
t
gco +
t
gcp(min))
(#22 + #30 + #37) + (#40) - (#55 + #42 + #57)
(0.3 + 1.6 + 2.2) + (0.3) - (0.9 + 1.4 + 0.8)
Clock (max) + Reg (hold) - Logic
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gh) - (
t
iobp +
t
grp4 +
t
20ptxor)
(#55 + #42 + #57) + (#41) - (#22 + #30 + #37)
(0.9 + 1.4 + 1.8) + (2.0) - (0.3 + 1.6 + 2.2)
Clock (max) + Reg(clock-to-out) + Output
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gco) + (
t
orp +
t
ob)
(#55 + #42 + #57) + (#42) + (#48 + #50)
(0.9 + 1.4 + 1.8) + (1.4) + (1.0 + 0.9)
t
h
t
co
1. Calculations are based upon timing specifications for the ispLSI 1048EA-170.
Table 2-0042/1048EA
v.2.0
9
LATTICE [ LATTICE SEMICONDUCTOR ]
