Specifications
ispLSI 1048EA
Internal Timing Parameters
1
PARAMETER
Outputs
#
DESCRIPTION
-170
-125
-100
MIN. MAX. MIN. MAX. MIN. MAX.
—
—
—
—
—
0.9
0.9
0.8
0.0
0.8
—
0.9
6.0
3.3
3.3
2.6
0.9
0.9
1.8
0.0
2.8
0.4
—
—
—
—
—
1.1
0.9
0.8
0.0
0.8
—
1.7
6.0
4.0
4.0
3.0
1.1
0.9
1.8
0.0
2.8
2.1
—
—
—
—
—
1.9
1.5
0.8
0.0
0.8
—
2.0
6.0
5.1
5.1
3.9
1.9
1.5
1.8
0.0
2.8
5.1
UNITS
t
ob
t
sl
t
oen
t
odis
t
goe
Clocks
50 Output Buffer Delay
51 Output Slew Limited Delay Adder
52 I/O Cell OE to Output Enabled
53 I/O Cell OE to Output Disabled
54 Global OE
55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
56 Clock Delay, Y1 or Y2 to Global GLB Clock Line
57 Clock Delay, Clock GLB to Global GLB Clock Line
58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
59 Clock Delay, Clock GLB to I/O Cell Global Clock Line
60 Global Reset to GLB and I/O Registers
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
gy0
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
Global Reset
t
gr
1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Table 2-0037A/1048EA
v.2.0
8
LATTICE [ LATTICE SEMICONDUCTOR ]
