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1048EA 参数 Datasheet PDF下载

1048EA图片预览
型号: 1048EA
PDF下载: 下载PDF文件 查看货源
内容描述: 在系统可编程高密度PLD [In-System Programmable High Density PLD]
分类和应用:
文件页数/大小: 14 页 / 183 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications ispLSI 1048EA  
Pin Description  
NAME  
PQFP / TQFP PIN NUMBERS  
DESCRIPTION  
I/O 0 - I/O 5  
21,  
22,  
28,  
35,  
41,  
53,  
59,  
67,  
73,  
86,  
92,  
99,  
23,  
29,  
36,  
42,  
54,  
60,  
68,  
74,  
87,  
93,  
100, 101,  
106, 107,  
119, 120,  
125, 126,  
24,  
30,  
37,  
43,  
55,  
61,  
69,  
75,  
88,  
94,  
25,  
31,  
38,  
44,  
56,  
62,  
70,  
76,  
89,  
95,  
102, 103,  
108, 109,  
121, 122,  
127, 128,  
26,  
32,  
39,  
45,  
57,  
63,  
71,  
77,  
90,  
96,  
Input/Output Pins - These are the general purpose I/O pins used by the  
logic array.  
I/O 6 - I/O 11  
I/O 12 - I/O 17  
I/O 18 - I/O 23  
I/O 24 - I/O 29  
I/O 30 - I/O 35  
I/O 36 - I/O 41  
I/O 42 - I/O 47  
I/O 48 - I/O 53  
I/O 54 - I/O 59  
I/O 60 - I/O 65  
I/O 66 - I/O 71  
I/O 72 - I/O 77  
I/O 78 - I/O 83  
I/O 84 - I/O 89  
I/O 90 - I/O 95  
27,  
34,  
40,  
52,  
58,  
66,  
72,  
85,  
91,  
98,  
104, 105,  
117, 118,  
123, 124,  
2,  
8,  
3,  
9,  
4,  
10,  
5,  
11,  
6,  
12,  
7,  
13  
GOE0, GOE1  
Global Output Enable input pins.  
Dedicated input pins to the device.  
64,  
47,  
114  
51  
111,  
84,  
115,  
110,  
IN 2, IN 4, IN 6-IN 11  
116, 14  
TDI  
20  
Input - Functions as an input pin to load programming data into the  
device and also is used as one of the two control pins for the ISP JTAG  
state machine.  
TMS  
TDO  
TCK  
46  
50  
78  
Input - Controls the operation of the ISP JTAG state machine.  
Output - Functions as an output pin to read serial shift register data.  
Input - Functions as a clock pin for the Serial Shift Register.  
RESET  
Y0  
19  
15  
83  
Active Low (0) Reset pin which resets all of the GLB and I/O registers in  
the device.  
Dedicated Clock input. This clock input is connected to one of the clock  
inputs of all of the GLBs on the device.  
Y1  
Dedicated Clock input. This clock input is brought into the clock  
distribution network, and can optionally be routed to any GLB on the  
device.  
Y2  
Y3  
80  
79  
Dedicated Clock input. This clock input is brought into the clock  
distribution network, and can optionally be routed to any GLB and/or  
any I/O cell on the device.  
Dedicated Clock input. This clock input is brought into the clock  
distribution network, and can optionally be routed to any I/O cell on the  
device.  
1,  
97,  
17,  
112  
33,  
82,  
49,  
65,  
81,  
GND  
Ground (GND)  
VCC  
16,  
18  
48,  
113  
VCC  
VCCIO  
Supply voltage for output drivers, 5V or 3.3V.  
Table 2-0002C/1048EA  
11