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1032E-80LJ 参数 Datasheet PDF下载

1032E-80LJ图片预览
型号: 1032E-80LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度可编程逻辑 [High-Density Programmable Logic]
分类和应用: 可编程逻辑
文件页数/大小: 16 页 / 213 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications ispLSI and pLSI 1032E  
Functional Block Diagram  
Figure 1. ispLSI and pLSI 1032E Functional Block Diagram  
RESET  
Input Bus  
Generic  
Logic Blocks  
(GLBs)  
Output Routing Pool (ORP)  
GOE 1/IN 5  
GOE 0/IN 4  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
I/O 47  
I/O 46  
I/O 45  
I/O 44  
C7  
C6  
C5  
C4  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
A0  
A1  
A2  
A3  
I/O 43  
I/O 42  
I/O 41  
I/O 40  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
Global  
Routing  
Pool  
I/O 39  
I/O 38  
I/O 37  
I/O 36  
C3  
C2  
C1  
C0  
I/O 8  
I/O 9  
(GRP)  
A4  
A5  
A6  
A7  
I/O 10  
I/O 11  
I/O 35  
I/O 34  
I/O 33  
I/O 32  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
*SDI/IN 0  
CLK 0  
CLK 1  
CLK 2  
IOCLK 0  
IOCLK 1  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
*MODE/IN 1  
Clock  
Distribution  
Network  
Output Routing Pool (ORP)  
Input Bus  
Megablock  
*ispEN/NC  
*ISP Control Functions for ispLSI 1032E Only  
The devices also have 64 I/O cells, each of which is The GRP has, as its inputs, the outputs from all of the  
directly connected to an I/O pin. Each I/O cell can be GLBs and all of the inputs from the bi-directional I/O cells.  
individually programmed to be a combinatorial input, All of these signals are made available to the inputs of the  
registered input, latched input, output or bi-directional GLBs. Delays through the GRP have been equalized to  
I/O pin with 3-state control. The signal levels are TTL minimize timing skew.  
compatible voltages and the output drivers can source 4  
Clocks in the ispLSI and pLSI 1032E devices are se-  
mA or sink 8 mA. Each output can be programmed  
lected using the Clock Distribution Network. Four  
independently for fast or slow output slew rate to mini-  
dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into  
mize overall output switching noise.  
the distribution network, and five clock outputs (CLK 0,  
Eight GLBs, 16 I/O cells, two dedicated inputs and one CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to  
ORP are connected together to make a Megablock (see route clocks to the GLBs and I/O cells. The Clock Distri-  
figure 1). The outputs of the eight GLBs are connected to bution Network can also be driven from a special clock  
a set of 16 universal I/O cells by the ORP. Each ispLSI GLB (C0 on the ispLSI and pLSI 1032E devices). The  
and pLSI 1032E device contains four Megablocks.  
logic of this GLB allows the user to create an internal  
clock from a combination of internal signals within the  
device.  
2