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1032E-80LJ 参数 Datasheet PDF下载

1032E-80LJ图片预览
型号: 1032E-80LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度可编程逻辑 [High-Density Programmable Logic]
分类和应用: 可编程逻辑
文件页数/大小: 16 页 / 213 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications ispLSI and pLSI 1032E  
1
Internal Timing Parameters  
-125  
MIN. MAX. MIN. MAX.  
-100  
2
PARAM.  
#
DESCRIPTION  
UNITS  
Inputs  
22 I/O Register Bypass  
23 I/O Latch Delay  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
iobp  
iolat  
iosu  
ioh  
0.3  
1.9  
0.3  
2.3  
24 I/O Register Setup Time before Clock  
25 I/O Register Hold Time after Clock  
26 I/O Register Clock to Out Delay  
27 I/O Register Reset to Out Delay  
28 Dedicated Input Delay  
3.0  
0.0  
3.5  
0.0  
ioco  
ior  
4.6  
4.6  
2.3  
5.0  
5.0  
2.7  
din  
GRP  
29 GRP Delay, 1 GLB Load  
30 GRP Delay, 4 GLB Loads  
31 GRP Delay, 8 GLB Loads  
32 GRP Delay, 16 GLB Loads  
33 GRP Delay, 32 GLB Loads  
ns  
ns  
ns  
ns  
ns  
t
t
t
grp1  
grp4  
grp8  
1.8  
2.0  
2.3  
2.8  
3.8  
1.9  
2.4  
2.4  
3.0  
4.2  
tgrp16  
tgrp32  
GLB  
34 4 Prod.Term Bypass Path Delay (Combinatorial)  
35 4 Prod. Term Bypass Path Delay (Registered)  
36 1 Prod.Term/XOR Path Delay  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
4ptbpc  
4ptbpr  
1ptxor  
20ptxor  
xoradj  
gbp  
3.9  
4.0  
3.6  
5.0  
5.0  
0.4  
5.3  
5.3  
4.6  
5.8  
6.3  
1.0  
t
t
t
t
t
t
t
t
t
t
t
t
37 20 Prod. Term/XOR Path Delay  
38 XOR Adjacent Path Delay 3  
39 GLB Register Bypass Delay  
40 GLB Register Setup Time before Clock  
41 GLB Register Hold Time after Clock  
42 GLB Register Clock to Output Delay  
43 GLB Register Reset to Output Delay  
44 GLB Prod.Term Reset to Register Delay  
45 GLB Prod. Term Output Enable to I/O Cell Delay  
46 GLB Prod. Term Clock Delay  
0.1  
4.5  
0.5  
5.8  
gsu  
gh  
gco  
2.3  
4.9  
3.9  
5.4  
4.0  
2.5  
6.2  
4.5  
7.2  
4.7  
gro  
ptre  
ptoe  
ptck  
2.9  
3.5  
ORP  
47 ORP Delay  
ns  
ns  
t
orp  
1.0  
0.0  
1.0  
0.0  
48 ORP Bypass Delay  
torpbp  
Table 2-0036A/1032E  
1. Internal Timing Parameters are not tested and are for reference only.  
2. Refer to Timing Model in this data sheet for further details.  
3. The XOR adjacent path can only be used by hard macros.  
7