ML145170
LANSDALE Semiconductor, Inc.
AC INTERFACE CHARACTERISTICS ( T = –40° to 85°C, C = 50 pF, Input t = t = 10 ns, unless otherwise noted.)
A
L
r
r
Figure
No.
V
V
Guaranteed
Limit
DD
Parameter
Serial Data Clock Frequency (Note: Refer to Clock t Below)
Symbol
Unit
f
clk
1
2.7
4.5
5.5
dc to 3.0
dc to 4.0
dc to 4.0
MHz
w
Maximum Propagation Delay, CLK to D
t
, t
1, 5
2, 6
2, 6
1, 5
1, 5
2.7
4.5
5.5
150
85
85
ns
ns
ns
ns
ns
out
PLH PHL
Maximum Disable Time, D Active to High Impedance
t
, t
PLZ PHZ
2.7
4.5
5.5
300
200
200
out
Access Time, D High Impedance to Active
t
t
PZL PZH
2.7
4.5
5.5
0 to 200
0 to 100
0 to 100
out
Maximum Output Transition Time, D
CL = 50 pF
t
, t
2.7
4.5
5.5
150
50
50
out
TLH THL
CL = 200 pF
2.7
4.5
5.5
900
150
150
Maximum Input Capacitance – D , ENB, CLK
C
–
–
10
10
pF
pF
in
in
Maximum Output Capacitance – D
C
out
out
TIMING REQUIREMENTS ( T = –40° to 85°C, Input t = tf= 10 ns, unless otherwise noted.)
A
r
Figure
V
V
Guaranteed
Limit
DD
No.
Parameter
Symbol
, t
Unit
Minimum Setup and Hold Times, D vs CLK
t
3
2.7
4.5
5.5
55
40
40
ns
in
su
h
Minimum Setup, Hold, and Recovery Times, ENB vs CLK
Minimum Inactive–High Pulse Width, ENB
Minimum Pulse Width, CLK
t
su
, t , t
rec
4
4
1
1
2.7
4.5
5.5
135
100
100
ns
ns
ns
µs
h
t
2.7
4.5
5.5
400
300
300
w(H)
t
w
2.7
4.5
5.5
166
125
125
Maximum Input Rise and Fall Times, CLK
t , t
2.7
4.5
5.5
100
100
100
r
f
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