ML145050, ML145051
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
D
out
Serial Data Output of the A/D Conversion Result(Pin 16)
DIGITAL INPUTS AND OUTPUT
This output is in the high-impedance state when CS is in
active high. When the chip recognizes a valid active low on
The various serial bit-stream formats for the ML145050/51
are illustrated in the timing diagrams of Figures 9 through 14.
Table 1 assists in selection of the appropriate diagram. Note
that the ADCs accept 16 clocks which makes them SPI (Serial
Peripheral Interface) compatible.
CS, D
is taken out of the high-impedance state and is driv-
out
en with the MSB of the previous conversion result. (For the-
first transfer after power-up, data on D is undefined for the
out
changes to the second most
entire transfer.) The value on D
out
significant result bit upon the first falling edge of SCLK. The
remaining result bits are shifted out in order, with the LSB
Table 1. Timing Diagram Selection
appearing on D
upon the ninth falling edge of SCLK. Note
out
that the order of the transfer is MSB to LSB. Upon the 10th
falling edge of SCLK, D is immediately driven low (if
No. of Clocks in Using
Serial Transfer
Interval
Figure
No.
Serial Transfer
CS
out
10
10
Yes
No
Don't Care
Don't Care
Shorter than Conversion
Shorter than Conversion
Longer than Conversion
Longer than Conversion
9
allowed by CS) so that transfers of more than 10 SCLKs read
zeroes as the unused LSBs.
When CS is held active low between transfers, D
en from a low level to the MSB of the conversion result for
three cases: Case 1 – upon the 16th SCLK falling edge if the
transfer is longer than the conversion time (Figure 14); Case 2
– upon completion of a conversion for a 16-bit transfer interval
shorter than the conversion (Figure 12); Case 3– upon comple-
tion of a conversion for a 10-bit transfer (Figure 10).
10
11
12
13
14
11 to 16
16
Yes
No
is driv-
out
11 to 16
16
Yes
No
CS
Active-Low Chip Select Input (Pin 15)
Chip select initializes the chip to perform conversions and
provides 3-state control of the data output pin (D ). While
out
Din
inactive high, CS forces D
to the high-impedance state and
out
Serial Data Input (Pin 17)
disables the data input (D ) and serial clock (SCLK) pins. A
in
The four-bit serial input stream begins with the MSB of the
analog mux address (or the user test mode) that is to be con-
verted next. The address is shifted in on the first four rising
edges of SCLK. After the four mux address bits have been
received, the data on D is ignored for the remainder of the
present serial transfer. See Table 2 in Applications Information.
high-to-low transition on CS resets the serial dataport and syn-
chronizes it to the MPU data stream. CS can remain active
during the conversion cycle and can stay in the active low state
for multiple serial transfers or CS can be in active high after
each transfer. If CS is kept active low between transfers, the
length of each transfer is limited to either 10 or 16 SCLK
cycles. If CS is in the inactive high state between transfers,
each transfer can be anywhere from 10 to16 SCLK cycles
long. See the SCLK pin description for a more detailed discus-
sion of these requirements.
in
SCLK
Serial Data Clock (Pin 18)
This clock input drives the internal I/O state machine to per-
On the ML145050/51 spurious chip selects caused by system form three major functions: (1) drives the data shift registers to
noise are minimized by the internal circuitry.
simultaneously shift in the next mux address from the D pin
in
Any transitions on the ML145050 CS pin are recognized as
valid only if the level is maintained for a setup time plus two
falling edges of ADCLK after the transition.
and shift out the previous conversion result on the D
pin,
out
(2) begins sampling the analog voltage onto the RCDAC as
soon as the new mux address is available, and (3) transfers
control to the A/D conversion state machine (driven by
Transitions on the ML145051 CS pin are recognized as valid
only if the level is maintained for about 2 ms after the transition. ADCLK) after the last bit of the previous conversion result has
been shifted out on the D pin.
out
NOTE
The serial data shift registers are completely static, allowing
SCLK rates down to the DC. There are some cases, however,
that require a minimum SCLK frequency as discussed later in
this section. SCLK need not be synchronous to ADCLK. At
least ten SCLK cycles are required for each simultaneous data
transfer. If the 16-bit format is used, SCLK can be one contin-
uous 16-bit stream or two intermittent 8-bit streams. After the
serial port has been initiated to perform a serial transfer*, the
new mux address is shifted in on the first
If CS is inactive high after the 10th SCLK cycle-
and then goes active low before the A/D conversion
is complete, the conversion is aborted and the chip
enters the initial state, ready for another serial trans-
fer/conversion sequence. At this point, the output
data register contains the result from the conversion
before the aborted conversion. Note that the last
step of the A/D conversion sequence is to update the
output data register with the result. Therefore, if CS
goes active low in an attempt to abort the conver-
sion too close to the end of the conversion
*The serial port can be initiated in three ways: (1) a recog-
nized CS falling edge, (2) the end of an A/D conversion if the
port is perform-ing either a 10-bit or a 16-bit “shorter-than-
conversion” transfer with CS active low between transfers,
and (3) the 16th falling edge of SCLK if the port is perform-
ing 16-bit “longer-than-conversion” transfers with CS active
low between transfers.
sequence, the result register may be corrupted and
the chip could be thrown out of sync with the
processor until CS is toggled again (refer to the AC
Electrical Characteristics in the spec tables).
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