ML145050, ML145051
LANSDALE Semiconductor, Inc.
CS
HIGH IMPEDANCE
D9
D
D9 – MSB
1
D8
A2
D7
A1
D6
D5
D4
D3
D2
D1
D0
out
2
3
4
5
6
7
8
9
10
1
SCLK
SAMPLE ANALOG INPUT
D
in
A3
A0
A3
MSB
EOC
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A/D CONVERSION
INTERVAL
INITIALIZE
RE-INITIALIZE
Figure 9. Timing for 10-Clock Transfer Using CS*
MUST BE HIGH ON POWER UP
CS
D
D9 – MSB
D8
A2
D7
A1
D6
D5
D4
D3
D2
D1
D0
D9
out
LOW LEVEL
SCLK
1
2
3
4
5
6
7
8
9
10
1
SAMPLE ANALOG INPUT
A3
A0
A3
D
in
MSB
EOC
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A/D CONVERSION
INTERVAL
INITIALIZE
Figure 10. Timing for 10-Clock Transfer Not Using CS*
NOTES:
1. D9, D8, D7, 0 , D0 = the result of the previous A/D conversion.
2. A3, A2, A1, A0 = the mux address for the next A/D conversion.
* This figure illustrates the behavior of the ML145051. The ML145050 behaves identically except there is no EOC signal and the conversion time
is 44 ADCLK cycles (user-controlled time).
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