ML145050, ML145051
LANSDALE Semiconductor, Inc.
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Guaranteed
Limit
Figure
Symbol
Parameter
Unit
1
f
Clock Frequency, SCLK
(10-bit xfer) Min
(11- to 16-bit xfer) Min
(10- to 16-bit xfer) Max)
0
MHz
Note 1
2.1
Note: Refer to t
, t below
wH wL
1
1
1
f
Clock Frequency, ADCLK
Note: Refer to t , t below
Minimum
Maximum
500
2.1
kHz
MHz
wH wL
t
Minimum Clock High Time
ADCLK
SCLK
190
190
ns
ns
wH
t
Minimum Clock Low Time
ADCLK
SCLK
190
190
wL
1, 7
1, 7
2, 7
2, 7
t
, t
Maximum Propagation Delay, SCLK to D
125
10
ns
ns
ns
PLH PHL
out
t
h
Minimum Hold Time, SCLK to D
out
t
, t
PLZ PHZ
Maximum Propagation Delay, CS to D
Maximum Propagation Delay, CS to D
High-Z
150
out
out
t
, t
PZL PZH
Driven
ML145050
ML145051
2 ADCLK cycles + 300
2.3
ns
µs
3
t
Minimum Setup Time, D to SCLK
in
100
0
ns
ns
ns
su
3
4, 7, 8
5
t
t
Minimum Hold Time, SCLK to D
h
d
in
Maximum Delay Time, EOC to D
out
Minimum Setup Time, CS to SCLK
(MSB)
ML145051
100
t
su
ML145050
ML145051
2 ADCLK cycles + 425
2.425
ns
µs
–
–
t
Minimum Time Required Between 10th SCLK Falling
Edge ( 0.8 V) and CS to Allow a Conversion
ML145050
ML145051
44
Note 2
ADCLK
cycles
CSd
t
Maximum Delay Between 10th SCLK Falling Edge
ML145050
ML145051
36
ADCLK
cycles
µs
CAs
(
2 V) and CS to Abort a Conversion
9
0
5
6, 8
1
t
h
Minimum Hold Time, Last SCLK to CS
Maximum Propagation Delay, 10th SCLK to EOC
Maximum Input Rise and Fall Times
ns
t
ML145051
2.35
µs
PHL
t , t
SCLK
ADCLK
D , CS
in
1
250
10
ms
ns
µs
r f
1, 4, 6 – 8
–
t
, t
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
300
ns
TLH THL
C
AN0 – AN10
55
15
pF
in
ADCLK, SCLK, CS, D
in
–
C
Maximum Three-State Output Capacitance
D
15
pF
out
out
NOTES:
1. After the 10th SCLK falling edge (≤ 2 V), at least 1 SCLK rising edge (≥ 2 V) must occur within 38 ADCLKs (ML145050) or 18.5 µs
(ML145051).
2. On the ML145051, a CS edge may be received immediately after an active transition on the EOC pin.
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