IT6605
In this double-edge triggering mode, PCLK frequency remains at the nominal pixel clock rate. The
halved data pins, however, run at a data rate double that of the nominal pixel clock rate. Each set of
data are clocked out by the rising edge and the falling edge alternatively. Overall one complete pixel is
output within one PCLK period. Figure 14 and Figure 15 give examples of 18-bit and 12-bit RGB 4:4:4
Dual-Edge Triggered output respectively.
blank
Pixel0
Pixel1
Pixel2
...
blank
QE[35:18]
QE[17:12]
QE[11:6]
QE[5:0]
PCLK
Gpix0
[5:0]
Rpix0
[11:6]
Gpix1
[5:0]
Rpix1
[11:6]
Gpix2
[5:0]
Rpix2
[11:6]
val
val
val
....
....
....
val
val
val
val
val
val
val
val
val
val
Bpix0
[11:6]
Rpix0
[5:0]
Bpix1
[11:6]
Rpix1
[5:0]
Bpix2
[11:6]
Rpix2
[5:0]
val
val
Bpix0
[5:0]
Gpix0
[11:6]
Bpix1
[5:0]
Gpix1
[11:6]
Bpix2
[5:0]
Gpix2
[11:6]
DE
H/VSYNC
Figure 14. 18-bit RGB 4:4:4 dual-edge triggered
blank
Pixel0
Pixel1
Pixel2
...
blank
QE[35:18]
QE[17:14]
QE[13:10]
QE[9:6]
QE[5:0]
PCLK
Gpix0
[3:0]
Rpix0
[7:4]
Gpix1
[3:0]
Rpix1
[7:4]
Gpix2
[3:0]
Rpix2
[7:4]
val
val
val
....
....
....
val
val
val
val
val
val
Bpix0
[7:4]
Rpix0
[3:0]
Bpix1
[7:4]
Rpix1
[3:0]
Bpix2
[7:4]
Rpix2
[3:0]
val
val
val
val
val
val
Bpix0
[3:0]
Gpix0
[7:4]
Bpix1
[3:0]
Gpix1
[7:4]
Bpix2
[3:0]
Gpix2
[7:4]
DE
H/VSYNC
Figure 15. 12-bit RGB 4:4:4 dual-edge triggered
Feb-2012 Rev:0.92 32/38
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