IT6605
RGB 4:4:4 and YCbCr 4:4:4 Triggered with 0.5X PCLK at Dual Edges
The bus mapping in this format is the same as that of RGB 4:4:4 and YCbCr 4:4:4 with Separate
Syncs. The only difference is that the output video clock (PCLK) is now halved in frequency. The data
are in turn to be latched in with both the rising and falling edges of the 0.5X PCLK.
blank
Pixel0
Pixel1
Pixel2
Pixel3
Pixel4
Pixel5
Pixel6
...
blank
val
val
val
val
val
val
val
val
val
val
Rpix0
Rpix1
Rpix2
Rpix3
Rpix4
Rpix5
Rpix6
....
....
....
val
QE[35:24]
QE[23:12]
QE[11:0]
PCLK
val
val
Gpix0 Gpix1 Gpix2 Gpix3 Gpix4 Gpix5 Gpix6
Bpix0 Bpix1 Bpix2 Bpix3 Bpix4 Bpix5 Bpix6
val
val
DE
H/VSYNC
Figure 16. 36-bit RGB 4:4:4 dual-edges triggered with 0.5X PCLK
blank
Pixel0
Pixel1
Pixel2
Pixel3
Pixel4
Pixel5
Pixel6
...
blank
val
val
val
val
val
val
val
val
val
val
Rpix0
Rpix1
Rpix2
Rpix3
Rpix4
Rpix5
Rpix6
....
val
val
val
QE[35:26]
QE[25:24]
QE[23:14]
QE[13:12]
QE[11:2]
QE[1:0]
PCLK
val
val
Gpix0 Gpix1 Gpix2 Gpix3 Gpix4 Gpix5 Gpix6
....
....
Bpix0
Bpix1
Bpix2
Bpix3
Bpix4
Bpix5
Bpix6
DE
H/VSYNC
Figure 17. 30-bit RGB 4:4:4 dual-edges triggered with 0.5X PCLK
Feb-2012 Rev:0.92 33/38
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ITE [ ITE TECH.INC. ]
