IT6605
System Design Consideration
The IT6605 is a very high-speed interface chip. It receives TMDS differential signals at as high as
2.25Gbps and output TTL signals at up to 148.5MHz with 36-bit data bus. At such high speeds any
PCB design imperfection could lead to compromised signal integrity and hence degraded
performance. To get the optimum performance the system designers sould follow the guideline below
when designing the application circuits and PCB layout.
1. Pin 54 (PVCC18) and Pin 53 (PVSS) should be supplied with clean power: ferrite-decoupled and
capacitively-bypassed, since they supply the power for the receiver PLL, which is a crucial block in
terms of receiving quality. Excess power noise might degrade the system performance.
2. It is highly recommended that all power pins are decoupled to ground pins via capacitors of 0.01uF
and 0.1uF. Low-ESL capacitors are prefered. Generally these capacitors should be placed on the
same side of the PCB with the IT6605 and as close to the pins as possible, preferably within 0.5cm
from the pins. It is also recommended that the power and ground traces run relatively short distances
and are connected directly to respecitve power and ground planes through via holes.
Figure 18. Layout example for decoupling capacitors.
3. The IT6605 supports 36-bit output bus running at as high as 148.5MHz. To maintain signal integrity
and lower EMI, the following guidelines should be followed:
A. Employ 4-layer PCB design, where a ground or power plane is directly placed under the
signal buses at middle layes. The ground and power planes underneath these buses should
be continuous in order to provide a solid return path for EM-wave introduced currents.
B. Whenever possible, keep all TTL signal traces on the same layer with the IT6605 and the
Feb-2012 Rev:0.92 34/38
www.ite.com.tw
ITE [ ITE TECH.INC. ]
