IT6605
by half compared from the previous YCbCr 4:2:2 formats, to either 8-bit, 10-bit or 12-bit. To
compensate for the halving of data bus, PCLK frequency is doubled. With the double-rate output clock,
luminance channel (Y) and chroma channels (Cb or Cr) are alternated. The syncs signals are
embedded in the Y-channel. Normally this format is used only for 480i, 480p, 576i and 576p. The
IT6605 supports CCIR-656 format of up to 720p or 1080i, with the doubled-rate clock running at
148.5MHz. CCIR-656 format supports embedded syncs only. Figure 10 and Figure 11 give examples
of 12-bit and 8-bit CCIR-656 respectively. Note that while "embedded syncs" implies that neither DE
nor H/VSYNC are required, the IT6605 optionally output these signals via proper register setting to
ease the design for some backend processors.
Figure 10. 12-bit CCIR-656
SAV
Pixel0 ~ Pixel1
Pixel2 ~ Pixel3
...
blank
QE[35:24]
QE[23:16]
QE[15:0]
PCLK
Cbpix0
[7:0]
Ypix0
[7:0]
Crpix0
[7:0]
Ypix1
[7:0]
Cbpix2
[7:0]
Ypix2
[7:0]
Crpix2
[7:0]
Ypix3
[7:0]
FF
00
00
XY
....
FF
Figure 11. 8-bit CCIR-656
Feb-2012 Rev:0.92 28/38
www.ite.com.tw
ITE [ ITE TECH.INC. ]
