IT6605
given for every pixel, while the two chroma channels are given alternatively on every other clock
period. The average bit amount of Y is twice that of Cb or Cr. Depending on the bus width, each
component could take on different lengths. The DE period should contain an even number of clock
periods. Figure 6 gives a timing example of 24-bit YCbCr 4:2:2.
Figure 6. 24-bit YCbCr 4:2:2 with separate syncs
blank
Pixel0
Pixel1
Pixel2
Pixel3
Pixel4
Pixel5
Pixel6
...
blank
Cbpix0
[7:0]
Crpix0
[7:0]
Cbpix2
[7:0]
Crpix2
[7:0]
Cbpix4
[7:0]
Crpix4
[7:0]
Cbpix6
[7:0]
val
....
val
val
val
val
val
QE[35:28]
QE[27:24]
QE[23:16]
QE[15:0]
PCLK
Ypix0
[7:0]
Ypix1
[7:0]
Ypix2
[7:0]
Ypix3
[7:0]
Ypix4
[7:0]
Ypix5
[7:0]
Ypix6
[7:0]
val
....
val
DE
H/VSYNC
Figure 7. 16-bit YCbCr 4:2:2 with separate syncs
Feb-2012 Rev:0.92 24/38
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