IT6605
i.e. embedded. Bus width could be 16-bit, 20-bit or 24-bit. Figure 8 gives a timing example of 24-bit
YCbCr 4:2:2 and Figure 9 that of 16-bit. Note that while "embedded syncs" implies that neither DE nor
H/VSYNC are required, the IT6605 optionally output these signals via proper register setting to ease
the design for some backend processors.
SAV
Pixel0
Pixel1
Pixel2
Pixel3
Pixel4
Pixel5
...
blank
val
Cbpix0
[11:0]
Crpix0
[11:0]
Cbpix2
[11:0]
Crpix2
[11:0]
Cbpix4
[11:0]
Crpix4
[11:0]
val
FF
val
00
val
00
val
XY
....
....
QE[35:24]
QE[23:12]
QE[11:0]
PCLK
Ypix0
[11:0]
Ypix1
[11:0]
Ypix2
[11:0]
Ypix3
[11:0]
Ypix4
[11:0]
Ypix5
[11:0]
FF
Figure 8. 24-bit YCbCr 4:2:2 with embedded syncs
Figure 9. 16-bit YCbCr 4:2:2 with embedded syncs
Feb-2012 Rev:0.92 26/38
www.ite.com.tw
ITE [ ITE TECH.INC. ]
