IS63LV1024
IS63LV1024L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns
-10 ns
-12 ns
Symbol
tWC
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
Write Cycle Time
CE to Write End
8
7
8
—
10
7
—
12
8
—
tSCE
—
—
—
ns
tAW
Address Setup Time to
Write End
—
8
—
8
—
ns
tHA
tSA
(1)
tPWE
1
(2)
tPWE
2
Address Hold from
Write End
0
—
0
—
0
—
ns
Address Setup Time
0
7
—
—
—
—
—
4
0
7
—
—
—
—
—
5
0
8
—
—
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
WE Pulse Width (OE High)
WE Pulse Width (OE Low)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
8
10
5
12
6
tSD
tHD
5
0
0
0
(2)
tHZWE
—
3
—
3
—
3
(2)
tLZWE
—
—
—
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
PWE1
PWE2
t
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. I
1/26/07
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
