®
IS61LV25616AL
ISSI
AC WAVEFORMS
(1 )
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW)
1
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
2
t
SA
t
t
HA
t
AW
t
PWE1
PWE2
3
t
WE
t
PBW
UB, LB
4
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
5
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
6
7
(1,2)
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle)
8
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
9
LOW
CE
t
AW
t
PWE1
WE
10
11
12
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
9
02/21/03
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
