®
IS61LV25616AL
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 3(WE Controlled. OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
t
PBW
UB, LB
HZWE
tLZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
tHD
DATAIN VALID
DIN
UB_CEWR3.eps
WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write) (1,3)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
tHA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
tHD
t
SD
tSD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/21/03
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
