®
ISSI
IS61LV12816L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns
-10 ns
Symbol
tWC
Parameter
Min. Max
Min. Max.
Unit
ns
Write Cycle Time
CE to Write End
8
7
7
—
—
—
10
8
—
—
—
tSCE
ns
tAW
Address Setup Time
to Write End
8
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
—
3
0
0
—
—
—
—
—
—
—
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSA
tPBW
tPWE1
tPWE2
tSD
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
6.5
6
8
7
6.5
4
8
5
tHD
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0
0
(3)
tHZWE
—
0
—
0
(3)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/27/05
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
