®
IS42S32200
ISSI
BURST READ/SINGLE WRITE
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic 1.
In this mode, all WRITE commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
AREADtobankmwillinterruptaREADonbankn, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.
2.InterruptedbyaWRITE(withorwithoutautoprecharge):
A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used two clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
CONCURRENTAUTOPRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMs support CONCURRENT AUTO PRECHARGE.
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
tRP - BANK n
t
RP - BANK m
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
D
OUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
DON'T CARE
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Read - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
tRP - BANK n
tRP - BANK m
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
D
OUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
Integrated Silicon Solution, Inc. — 1-800-379-4774
29
ADVANCE INFORMATION Rev. 00B
08/14/03
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
