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IC61C1024-15KI 参数 Datasheet PDF下载

IC61C1024-15KI图片预览
型号: IC61C1024-15KI
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, SOJ-32]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 11 页 / 147 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IC61C1024  
IC61C1024L  
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)  
(2)  
-12  
-15 ns  
-20 ns  
-25 ns  
Symbol Parameter  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC  
Read Cycle Time  
12  
3
12  
12  
12  
6
15  
3
15  
15  
15  
7
20  
3
20  
20  
20  
9
25  
3
25  
25  
25  
9
tAA  
Address Access Time  
Output Hold Time  
CE1 Access Time  
CE2 Access Time  
OE Access Time  
tOHA  
tACE1  
tACE2  
tDOE  
0
0
0
0
(3)  
tLZOE  
OE to Low-Z Output  
OE to High-Z Output  
6
6
7
10  
10  
20  
(3)  
tHZOE  
0
0
0
0
tLZCE1(3) CE1 to Low-Z Output  
tLZCE2(3) CE2 to Low-Z Output  
2
7
2
8
3
9
3
2
2
3
3
(3)  
tHZCE  
CE1 or CE2 to High-Z Output  
0
0
0
0
(4)  
tPU  
CE1 or CE2 to Power-Up  
0
12  
0
12  
0
18  
0
(4)  
tPD  
CE1 or CE2 to Power-Down  
Notes:  
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V  
and output loading specified in Figure 1.  
2. -12 ns device for IC61C1024 only.  
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.  
4. Not 100% tested.  
AC TEST CONDITIONS  
Parameter  
Input Pulse Level  
Input Rise and Fall Times  
Unit  
0V to 3.0V  
3 ns  
Input and Output Timing  
and Reference Level  
1.5V  
Output Load  
See Figures 1 and 2  
AC TEST LOADS  
480  
480  
5V  
5V  
OUTPUT  
OUTPUT  
255 Ω  
255 Ω  
30 pF  
Including  
jig and  
5 pF  
Including  
jig and  
scope  
scope  
Figure 1  
Figure 2  
6
Integrated Circuit Solution Inc.  
AHSR008-0B 10/18/2001