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IC61C1024-15KI 参数 Datasheet PDF下载

IC61C1024-15KI图片预览
型号: IC61C1024-15KI
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, SOJ-32]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 11 页 / 147 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IC61C1024  
IC61C1024L  
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low  
Power)  
(3)  
-12 ns  
Min.  
-15 ns  
Min.  
-20 ns  
-25 ns  
Symbol Parameter  
Max.  
7
Max.  
7
Min.  
Max.  
Min.  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tWC  
Write Cycle Time  
12  
10  
10  
10  
0
15  
12  
12  
12  
0
20  
15  
15  
15  
0
25  
20  
20  
20  
0
tSCE1  
tSCE2  
tAW  
CE1 to Write End  
CE2 to Write End  
Address Setup Time to Write End  
Address Hold from Write End  
Address Setup Time  
tHA  
tSA  
0
0
0
0
(4)  
tPWE  
tSD  
WE Pulse Width  
10  
7
10  
8
12  
10  
0
15  
12  
0
Data Setup to Write End  
Data Hold from Write End  
WE LOW to High-Z Output  
WE HIGH to Low-Z Output  
tHD  
0
0
(5)  
tHZWE  
2
2
2
10  
2
12  
(5)  
tLZWE  
Notes:  
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V  
and output loading specified in Figure 1.  
2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to  
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the  
rising or falling edge of the signal that terminates the Write.  
3. -12 ns device for IC61C1024 only.  
4. Tested with OE HIGH.  
5. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.  
8
Integrated Circuit Solution Inc.  
AHSR008-0B 10/18/2001