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IC61C1024-15KI 参数 Datasheet PDF下载

IC61C1024-15KI图片预览
型号: IC61C1024-15KI
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, SOJ-32]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 11 页 / 147 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IC61C1024  
IC61C1024L  
AC WAVEFORMS  
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )  
t
WC  
VALID ADDRESS  
SCE  
ADDRESS  
CE  
t
SA  
t
t
HA  
t
AW  
t
t
PWE1  
PWE2  
WE  
t
HZWE  
t
LZWE  
HIGH-Z  
DATA UNDEFINED  
DOUT  
t
SD  
t
HD  
DATAIN VALID  
DIN  
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)  
t
WC  
ADDRESS  
OE  
VALID ADDRESS  
t
HA  
LOW  
CE  
t
AW  
t
PWE1  
WE  
t
SA  
t
HZWE  
t
LZWE  
HIGH-Z  
DATA UNDEFINED  
DOUT  
t
SD  
t
HD  
DATAIN VALID  
DIN  
Notes:  
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states  
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced  
to the rising or falling edge of the signal that terminates the Write.  
2. I/O will assume the High-Z state if OE = VIH.  
Integrated Circuit Solution Inc.  
AHSR008-0B 10/18/2001  
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