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IC42S16800D-7TL 参数 Datasheet PDF下载

IC42S16800D-7TL图片预览
型号: IC42S16800D-7TL
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆×8 , 8Meg X16 128兆位同步DRAM [16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 62 页 / 530 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS42S81600D, IS42S16800D  
READS  
READ COMMAND  
READburstsareinitiatedwithaREADcommand,asshown  
in the READ COMMAND diagram.  
CLK  
Thestartingcolumnandbankaddressesareprovidedwiththe  
READ command, and auto precharge is either enabled or  
disabledforthatburstaccess.Ifautoprechargeisenabled,the  
row being accessed is precharged at the completion of the  
burst.ForthegenericREADcommandsusedinthefollowing  
illustrations, auto precharge is disabled.  
HIGH  
CKE  
CS  
RAS  
During READ bursts, the valid data-out element from the  
startingcolumnaddresswillbeavailablefollowingtheCAS  
latencyaftertheREADcommand. Eachsubsequentdata-  
outelementwillbevalidbythenextpositiveclockedge.The  
CAS Latency diagram shows general timing  
for each possible CAS latency setting.  
CAS  
WE  
Upon completion of a burst, assuming no other commands  
havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst  
will continue until terminated. (At the end of the page, it will  
wrap to column 0 and continue.)  
COLUMN ADDRESS  
AUTO PRECHARGE  
A0-A9  
A11  
Data from any READ burst may be truncated with a subse-  
quentREADcommand, anddatafromafixed-lengthREAD  
burst may be immediately followed by data from a READ  
command. In either case, a continuous flow of data can be  
maintained.Thefirstdataelementfromthenewburstfollows  
eitherthelastelementofacompletedburstorthelastdesired  
data element of a longer burst which is being truncated.  
A10  
NO PRECHARGE  
BANK ADDRESS  
BA0, BA1  
Note: A9 is "Don't Care" for x16.  
ThenewREADcommandshouldbeissuedxcyclesbefore  
the clock edge at which the last desired data element is  
valid, where x equals the CAS latency minus one. This is  
shown in Consecutive READ Bursts for CAS latencies of  
twoandthree;dataelementn+3iseitherthelastofaburst  
of four or the last desired of a longer burst. The 128Mb  
SDRAM uses a pipelined architecture and therefore does  
not require the 2n rule associated with a prefetch architec-  
ture. AREADcommandcanbeinitiatedonanyclockcycle  
following a previous READ command. Full-speed random  
readaccessescanbeperformedtothesamebank,asshown  
in Random READ Accesses, or each subsequent READ  
may be performed to a different bank.  
The DQM input is used to avoid I/O contention, as shown  
in Figures RW1 and RW2. The DQM signal must be  
asserted (HIGH) at least three clocks prior to the WRITE  
command(DQMlatencyistwoclocksforoutputbuffers)to  
suppress data-out from the READ. Once the WRITE com-  
mandisregistered,theDQswillgoHigh-Z(orremainHigh-  
Z), regardless of the state of the DQM signal, provided the  
DQM was active on the clock just prior to the WRITE  
command that truncated the READ command. If not, the  
second WRITE will be an invalid WRITE. For example, if  
DQMwasLOWduringT4inFigureRW2,thentheWRITEs  
at T5 and T7 would be valid, while the WRITE at T6 would  
be invalid.  
Data from any READ burst may be truncated with a  
subsequent WRITE command, and data from a fixed-length  
READ burst may be immediately followed by data from a  
WRITE command (subject to bus turnaround limitations).  
The WRITE burst may be initiated on the clock edge  
immediatelyfollowingthelast(orlastdesired)dataelement  
from the READ burst, provided that I/O contention can be  
avoided. In a given system design, there may be a possi-  
bility that the device driving the input data will go Low-Z  
before the SDRAM DQs go High-Z. In this case, at least a  
single-cycledelayshouldoccurbetweenthelastreaddata  
and the WRITE command.  
The DQM signal must be de-asserted prior to the WRITE  
command (DQM latency is zero clocks for input buffers) to  
ensure that the written data is not masked.  
Afixed-lengthREADburstmaybefollowedby, ortruncated  
with, aPRECHARGEcommandtothesamebank(provided  
that auto precharge was not activated), and a full-page burst  
may be truncated with a PRECHARGE command to the  
samebank.ThePRECHARGEcommandshouldbeissued  
xcyclesbeforetheclockedgeatwhichthelastdesireddata  
elementisvalid,wherexequalstheCASlatencyminusone.  
ThisisshownintheREADtoPRECHARGEdiagramforeach  
28  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. E  
07/28/08  
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