IS42S81600D, IS42S16800D
CAS Latency
Operating Mode
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
ThenormaloperatingmodeisselectedbysettingM7andM8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
If a READ command is registered at clock edge n, and the
latencyism clocks, thedatawillbeavailablebyclockedge
n+m.TheDQswillstartdrivingasaresultoftheclockedge
one cycle earlier (n + m - 1), and provided that the relevant
access times are met, the data will be valid by clock edge
n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ
commandisregisteredatT0andthelatencyisprogrammed
totwoclocks,theDQswillstartdrivingafterT1andthedata
willbevalidbyT2,asshowninCASLatencydiagrams.The
AllowableOperatingFrequencytableindicatestheoperat-
ing frequencies at which each CAS latency setting can be
used.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
appliestobothREADandWRITEbursts;whenM9=1, the
programmedburstlengthappliestoREADbursts,butwrite
accesses are single-location (nonburst) accesses.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
Reservedstatesshouldnotbeusedasunknownoperationor
incompatibility with future versions may result.
-6
125
100
133
166
143
—
-7
-75E
CAS LATENCY
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
DOUT
t
LZ
tOH
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
DOUT
tLZ
tOH
CAS Latency - 3
DON'T CARE
UNDEFINED
26
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
