IS42S16100E, IC42S16100E
Read Cycle / Precharge Termination
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
COLUMN m
ROW
ROW
ROW
A0-A9
t
t
t
AH
AH
ROW
A10
A11
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
t
AS
BANK 1
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
DQ
t
AC
t
AC
t
AC
tHZ
t
OH
t
OH
tOH
D
OUT
m
D
OUT m+1
D
OUT m+2
t
LZ
t
RCD
t
CAC
t
RQL
RP
t
RCD
RAS
RP
t
RAS
RC
t
t
t
t
<
PRE 0>
READ 0
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
74
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08