IS42S16100E, IC42S16100E
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
tCKS
t
CKS
tCKH
t
CL
t
CK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
t
AH
(1)
COLUMN m
AUTO PRE
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
t
t
AH
AH
NO PRE
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
tCS
t
CH
t
QMD
DQM
DQ
tAC
t
AC
t
OH
t
OH
D
OUT
m
D
OUT m+1
t
LZ
t
HZ
t
RCD
t
CAC
t
RAS
RC
tRP
t
<
SPND>
<
SPND>
<
PRE
PALL
>
<ACT>
<
READ
>
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
72
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08